1. Field of the Invention
This invention relates generally to the method and system of testing the integrated circuits (ICs). More particularly, this invention relates to a high speed real time testing by employing a new testing technique which utilizes a different testing configuration such that the requirements that the testing stimuli must first be generated or stored for input as a sequence of testing patterns or testing vectors may be eliminated.
2. Description of the Prior Art
As the integrated circuits (ICs) become more complicate with higher level of integration and increasingly faster operational speed, the traditional technique of IC testing by pre-storing in high speed memory a plurality of `test pattern signals` and then supplying these pattern signals through different drivers to corresponding terminal pins at different times becomes too expensive and complicate to be practically useful. Specifically, these type of testing techniques often can not achieve the necessary `fault coverage` as increasingly more functions are being integrated into a single IC. High speed IC testing with high pin count, particularly for the application specific ICs (ASICs), usually requires testing equipments cost millions of dollars and consumes many man-months of testing engineers' efforts for each specific design. These highly sophisticate testing equipments and long-hours of engineering efforts are required because of the needs to (1) generate large amount of `test pattern signals`, or often referred to as `test vectors` or `input stimulus`, for each input pin, (2) perform an `off-line` simulation analysis with the test pattern signals as input to calculate a plurality of `predicted output signals` from each of output pins and stored the predicted output signals in the memory of the tester, (3) control the timing and sequence for transmitting and inputting each of these test vectors to each input pin, (4) collect a plurality of output signals from each output pin at exact timing, and (5) compare each of the output signals with the predicted `correct` output signal at exact time and sequence to determine if the device under test (DUT) performs each tested function according to the design.
As the ICs now include more input, output and input/output (I/O) pins and operating at higher speed, testing of these ICs becomes even more complex and expensive. A very complicate simulation program has to be developed to model the high speed functioning of the circuits embodied in the DUT. Large amount of input data and simulated output data have to be generated and stored as the `test pattern signals` for each input pin and `predicted output signals` for each output pin. The test pattern signals are to be controlled for transmitting and then inputting to each input pin at exact time and sequence at high speed. Meanwhile, the output signals from each output pin are to be collected, stored or processed, also at very high speed to complete the test functions. Tremendous resources, including man-power, expenditures for testing equipments, and testing software developments are demanded by such a testing operation.
Many different techniques are disclosed in prior U.S. patents in attempt to reduce the costs and efforts, or to improve the performance levels of the IC testing operations. Takeuchi discloses in U.S. Pat. No. 4,523,312 (issued on Jun. 11, 1985) a test configuration wherein a plurality of low pass filters are used to improve the `rise and fall characteristics` of the test pattern signals. The errors which may be introduced due to grounding capacities of connector lines and the IC socket may be reduced by the use of the low pass filters as disclosed by Takeuchi. In another U.S. Pat. No. 4,771,428 (issued on Sep. 13, 1988), Acuff et al. discloses a testing computer which stores a plurality of test vectors representing stimulus signals for applying to circuit. The testing computer also stored a plurality of data representing the responsive data to be sensed from the circuit The stored test vectors are then applied through a driver associated with each input of the circuit to be tested. The driver can generate an output signal which can be either a high or low state in response to the input stimulus signals and a floating state in response to data representing the response signals. Response signals from the device to be tested are compared to the data representing response signals to determine the occurrence of a fault.
Eichelberger et al. disclose in U.S. Pat. No. 4,801,870 a method for testing a very large scale integrated circuit (VLSI), particularly, the Level Sensitive Scan Design (LSSD) devices, by applying in parallel differently configured sequences of pseudo-random patterns to each of the input terminals of the device under test. The output response data are then collected from each of the output terminals in parallel and combined into a `signature`. The collected signatures are then compared with predicted signatures generated from a computer simulation analysis. The input stimulus signals are then altered in a predetermined fashion as a function of the structure of the DUT by applying different weights to the input signals for input to each input terminals. The above testing techniques as disclosed by Takeuchi, Acuff et al., and Eichelberger et al. are useful in either improving the accuracy of the test operation or to provide better methods to detect device failures. However, the basic mode of operation, i.e., to first generate, store, and apply testing vectors to the DUT and then compare the responses with predicted simulation results for fault detection, does not provide a solution to the difficulty currently faced by the art of IC testing. This method is too time consuming, expensive and complicate for application to the modern IC designs. With the number of pins, the faster speed and the level of integration in combining so many functions in a single IC, this traditional method of testing is not suitable to achieve the goal of functionality test in an economical and effective manner.
Several more recent U.S. patents apply the same basic testing technique and similar system configuration with (1) improvements over the control of the input signal timing, i.e., U.S. Pat. No. 4,893,072 by Matsumoto, (2) reduction of expenditure in testing by including `testing component` as part of the circuits on an IC, i.e., U.S. Pat. No. 4,961,053 by Krug, (3) increasing the test speed by providing high speed clock signals, i.e., U.S. Pat. No. 5,177,440 by Walker, III et al., (4) lower the cost for testing the ASICs by providing dedicated ASIC tester with its own microprocessor and random access memory (RAM) for storing the testing vectors and predicted responses, i.e., U.S. Pat. No. 5,243,274 by Kelsey et al., and (5) applying personal computer (PC) workstation to remotely control the generation of the stimulus and collection of the responses by the use of four-channel Test Access Port All these techniques can achieve to a certain extent a higher speed or accuracy, cost reduction, or convenience and efficiency of the testing operations. However, in this conventional approach, due to the heavy burden in requiring the very complex processes of controlling the generation, storing, inputting and processing tremendous amount of input data, i.e., testing pattern signals, and output data, i.e, the response signals, the IC functional tests remain to be one of the most expensive, time consuming and difficult tasks.
Therefore, there is still a demand in the art of IC testing for a new technique and system configuration which can simplify the IC testing processes thus minimizing the requirements for expensive testing equipments, the long-hours of engineers' efforts for testing pattern generating and output signal simulation, the memory required for the storage of the testing input and output data, and the highly sophisticated control of exact timing in transmitting and collecting of these data.